In the field of power integrated circuits much work has been done in the development of power transistors. Advancements were made enabling LDMOS power transistors (lateral double diffused MOS transistor) to exhibit low "on-resistance" (RDSon) and high breakdown capability concurrently through a reduced surface field (RESURF) technique (J. A. Appels and H. M. J. Vaes, "High Voltage Thin Layer Devices (RESURF Devices)", IEDM Tech. Digest, pp. 238-241, 1979).
In IC design, semiconductor die area is crucial. Generally, an increase in transistor area results in a decrease in transistor RDSon. A trade-off between transistor performance and device cost becomes a crucial design constraint. This issue has driven research into new transistor structures that provide low RDSon while simultaneously minimizing transistor area. One proposed improvement has been the development of a trench DMOS transistor (Ueda, Daisuke; Takagi, Hiromitsu; Kano, Gota; "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process", IEEE Transactions on Electron Devices, Vol. ED-34, No. 4, April 1987). Other improvements are needed.
It is an object of this invention to provide a high voltage power transistor exhibiting improved RDSon performance while reducing transistor area. It is another object of this invention to provide a power transistor of trench DMOS technology type, having its source isolated from its substrate. Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following description and drawings.